1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a built-in programmable divider.
2. Description of the Prior Art
As for a prior art semiconductor integrated circuit with a built-in programmable divider, well-known is a semiconductor integrated circuit which compares phases of a frequency divided signal obtained by dividing an external input signal and a reference signal in order to output a phase difference comparison signal (referred to as "PLL semiconductor integrated circuit" hereinafter).
FIG. 12 is a block diagram showing a system architecture of a first half portion of a prior art television receiver which employs a PLL semiconductor integrated circuit 1. A signal of a desired channel in television signals received by an antenna 15 is amplified by a high-frequency amplifying circuit 14, and after it is converted into an intermediate-frequency signal by a mixer 16, the signal is amplified by an intermediate-frequency amplifying circuit 17 and outputted to the following stage. The mixer 16 receives an output signal of a voltage control oscillator 12 in a PLL circuit 11 as a local oscillation signal. In the PLL circuit 11, a closed loop is composed of the voltage control oscillator 12, the PLL semiconductor integrated circuit 1 and a low-pass filter 13; thereby a frequency of an output signal of the voltage control oscillator 12 is fixed.
The PLL semiconductor integrated circuit 1 includes, as shown in FIG. 13, a programmable divider 2 and a phase comparator 3. An output signal of the voltage control oscillator 12 is applied through an input terminal P1 to the programmable divider 2. The programmable divider 2 divides the frequency of the output signal of the voltage control oscillator 12 with a frequency dividing ratio determined in accordance with a command from an external device 20, such as a computer and the like, to output a frequency divided signal. The phase comparator 3 compares the frequency divided signal with a reference signal applied through an input terminal P2 in phase to output the resultant comparison signal through an output terminal P3 to the low-pass filter 13. Reference symbols, V.sub.DD and GND, denote a supply voltage applying terminal and a ground terminal, respectively.
The frequency dividing ratio employed in the programmable divider 2 is determined as follows: First, an enable signal "HIGH" is inputted through an enable terminal P4 from the external device 20; and then, a clock signal and data for determining a frequency dividing ratio are inputted through a clock input terminal P5 and a data input terminal P6, respectively. The shift register 8 sequentially reads data for determining a frequency dividing ratio in accordance with the fall of the clock signal and transfers the data for determining a frequency dividing ratio to a data latch circuit 7 in parallel. When the enable signal from the enable terminal P4 turns to "LOW", the data latch circuit 7 latches the data for determining a frequency dividing ratio at the last transition to apply the data to the programmable divider 2; in accordance with the data for determining a frequency dividing ratio, the programmable divider 2 determines a frequency dividing ratio.
Although the PLL circuit 11 in the television receiver has been described, PLL circuits employed in a transmitter and receiver of a telephone of an automobile or a cordless telephone, a transponder for satellite communication and the like are also similar in system architecture for the purpose of keeping constant frequency and phase of an output of the voltage control oscillator 12.
The prior art PLL semiconductor integrated circuit is structured as previously mentioned, where the shift register 8 and data latch circuit 7 and the enable terminal P4, clock input terminal P5 and data input terminal P6 for inputting data to them are essential for determining a frequency dividing ratio in the programmable divider 2.
As for the transponder for satellite communication and the like, however, a proposition is made that silicon, which is a general semiconductor material, should be replaced with compound semiconductor to make the PLL semiconductor integrated circuit 1. In this case, since the compound semiconductor is expensive, it is desirable that the PLL semiconductor integrated circuit 1 is miniaturized as much as possible to reduce the price. In the prior art PLL semiconductor integrated circuit 1 as shown in FIG. 13, however, a miniaturization is difficult because the shift register 8, data latch circuit 7, enable terminal P4, clock input terminal P5 and data input terminal P6 are essential.